By using basic graph theory, we will try to find the complementary networks in a CMOS circuit. Our goal here is not to analyze graph theory or Euler paths but to understand and quickly determine said networks. This will be quicker and more effective by solving an example.

Let us have the following Nmos network:

Initially we will design the graph of the Nmos network. First of all, we need to place all the nodes that occur. There is one in Y(output), one in GND and 2 in between, where A,B,C and C,B,E are connected respectively.

After finishing this step, we can proceed to connect the nodes, assuming that every connection represents a transistor.

So, now we have to design the Pmos network. In the existing graph we place the Vdd node and the Y node an both the sides of the graph. We will also place a node in every “closed path” we find, as it is seen in the following picture.

**Note:**As long as Vdd and Y are both at the sides of the graph, it doesn’t matter if Vdd is in the right side and Y on the left or vice versa.

Having done this, the only thing left is to connect all the complementary nodes with each other by crossing each Nmos connection only **once**.

If we “reverse” the Pmos graph to get the network we will have something like this:

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