An article by Dimitrios Dimopoulos under the supervision of Professor K. Efstathiou
It is almost impossible not to get involved with ftdi chips as it is a very easy way to achieve serial communication nowadays. So, the Applied Electronics Laboratory from the department of Electrical and Computer Engineering (University of Patrai, Greece) has used to some extend the FT4232H mini module. Considering that most of the times it is not required to take the advantage of all the features provided by this module, the next rational move was to use the FT232RL chip which requires significantly smaller amount of peripheral components for providing similar (even more) functionalities to these the one port of FT4232 provides!
The primary aim of this project is to examine the FT232R’s capability to generate a stable clock frequency, which is required to applications related to data acquisition,in bit bang mode (more information on bit bang mode in the references). In most of these applications the stability of the sampling frequency is of crucial importance. In this project it will be revealed that FT232R is not able to comply with this demand whereas its successor, the FT4232 chip does.
The product was tested using this visual basic interface which we developed [and can be found here ]. So, what it really does is simply finding the first FTDI device connected to a PC (our module in this situation) and setting it to synchronous bit bang mode. It then uses a 32k buffer which is filled by alternating 0’s and 1’s which will be our data sent. Our graphical user interface gives us the option to choose how many bytes will be sent and at what rate.
So let us begin the comparison by examining the 4232H module.
In the first picture you can see that we have about 3.3V (which can be considered “logic 1”). According to our explanation of the test application if the number of bits are incremented by 1 then we will have “logic 0” which is indeed 0 volts.
If we increase the number of bytes by 1 again then it will be “1” and so on.
At 15 bytes we will have this.
Continuing at 32 bytes this will be our output.
In a similar fashion at 60 bytes we will have
and finally at 90 bytes we can clearly see this .
Again, tampering with the division gives us the following results:
for 10 bytes sent at default rate,
for 10 bytes and division 10x and
for 10 bytes at 20x division. Nothing problematic so far, so we can switch to the FT232RL.
Before we begin with the FT232RL chip , we will provide the schematic as well as the pcb of the module we made.It can be found here (Protell compatible).
The procedure is quite similar. We will initially try to observe the function of the FT232RL as the number of bytes and the division increase. Starting at 0 bytes all is normal.
At 17 bytes this will be the result.
Everything’s ok by now. But as we continue and reach the threshold of 23 bytes we find something strange to start happening. As seen in the video
we realize that our data is not sent correctly. We can clearly see that the rate fluctuates at a certain point, which can cause to ruin communication. Continuing at 36 bytes we see that the problem persists .
At 67 bytes the problem is further aggravated
and at 84 bytes our waveform is virtually split in half
as it is more evident at 90 bytes .
Finally, by tampering with the division we also see that there is some sort of error in our serial communication as shown by the following pictures and videos.
Photo at 10 bytes 0x division , video at 10 bytes division 3x
and video at 10 bytes division 4x
To sum up we have concluded that (according to our experimental results) this product cannot comply with our demand of stable clock frequency. Any comments on the topic are more than welcome!
- Please choose the highest quality possible in the youtube videos.
- Oscilloscope used: TiePie Handyscope model HS3@50MHz , 5k sampling, resolution @12bits.
- FT4232H Mini Module USB Hi-Speed Module Datasheet
- FT232R USB UART IC Datasheet
- D2XX Programmer’s Guide
- Bit Bang Modes for the FT232R and FT245R